IP Cores

Minerva LLC offers to customers list of IP Core. Each IP Core is ready to use and accompanied by set of verification tools (testbench, test vectors) and detailed product description, including how to integrate the core into the system of the customer. By default, the IP Cores made to run on FPGA but, on request, it can be adapted for ASIC.

SATA Controller IP Core

Video Output Port IP Core

CABAC Encoder IP Core

CABAC Decoder IP Core

Low latency AVC Encoder IP Core

UpScaler IP Core

 

Universal dynamically configurable codecs:

  • RS Turbo Wimax/DVB codec (BCJR decoding algorithm in the MaxLogMap version)
  • RSC2 Turbo DVB2 codec (BCJR decoding algorithm in the MaxLogMap version)
  • WiMAX LDPC codec (BP/Layered BP decoding algorithm in the Normalized Min-Sum version)
  • NASA GSFC LDPC codec (STD 9100). BP/Layered BP decoding algorithm in the Normalized Min-Sum version)
  • Turbo CCSDS 131.0-B-3 codec (BCJR decoding algorithm in the MaxLogMap version)
  • LDPC 3GPP TS 38.212 v15.7.0. Layered BP decoding algorithm in the Normalized Min-Sum version
  • 4D-8PSK CCSDS 413.0-G-2
  • Dynamically configurable high-performance Reed-Solomon codec.
  • Dynamically configurable BCH codec.

Digital Connectivity hardware

Many years of expertise in the development of complex electronic equipment allows us to offer our customers professional hardware, which provides a solution to such problems as:

 

  • Capturing the digital data stream
  • Transformation of data formats in real time
  • Data flow analysis
  • Interfaces conversion and mating

The company's equipment can be used in the preparation of broadcast digital television, analyzing the quality of streaming video and audio, research, etc.

uScio FMC Carrier USB 3.0 Board

Video IO FMC Mezzanine board (Broadcast/HDCCTV)

Video IO FMC Mezzanine board (LVDS/Camera link)

Multichannel ultrasonic data asquisition subsystem for NDT