CABAC encoder IP Core is designed to perform a context-adaptive binary arithmetic coding. High performance combined with a compact size make the core of the best coprocessor to accelerate video encoding in the embedded systems.

CABAC Encoder IP Core - RTL implementation lossless algorithms CABAC (Context-Adaptive Binary Arithmetic Coding). IP core is designed for hardware acceleration of entropy arithmetic coding for video compression format AVC (H.264).

• Fully complies with ISO / IEC 14496-10/ITU-T H.264;
• Profile: Main;
• High performance. Bit rates - up to 50 Mbit/s at a clock frequency of 180 MHz;
• Hardware initialization and binarization contexts;
• Compact core size. Can be used for FPGA low price range.

The IP Core is available either netlist (netlist) or in source code, and includes everything necessary for a successful implementation of the project customer. The netlist  includes:

 

• Synthesized netlist for the specified device FPGA;
• Testbench and bit accurate model;
• Place @ Rout script;
• The script for the simulation;
• Documentation, including detailed specifications and instructions for the integration of the project member.

 

 

For further technical information please send request to info@minerva-tech.com.

 

For purchasing or licensing IP Core please contact to  sales@minerva-tech.com.