News

25.04.2024 As part of the V FPGA Developers Conference (FPGA-Systems 2024.1), we present a report on the topic: "Highly efficient hardware implementation of the h264/AVC video codec".


The presentation examines the existing solutions of high-performance video codecs capable of compressing and transmitting with the maximum possible the quality of the video image over the network or radio channel. The report presents a highly efficient and compact hardware implementation of the h264/AVC codec for embedded systems, designed for encoding video in real time with low latency. During the presentation, it is planned to demonstrate the codec on the developer's board based on the FPGA XC7Z020.


The report will be of interest to everyone involved in the development of digital devices in the field of digital video. The conference program is available at the organizer's website

10.11.2023 The development of a data asquisition system for testing the operability of specialized matrix integrated circuits MIC 1024 has been completed.


The data asquisition system is designed to test the operability of specialized matrix integrated circuits MIC1024 and hybrid sensor assemblies based on them. The developed system allows you to monitor the performance of the MIC1024 chip after each technological stage of creating a hybrid sensor assembly. The operability check is performed both on microchips consisting of a 150 mm waffels using a manual MPI TS150 probe station, and on microchips installed on a printed circuit board.Technical characteristics in more detail


9.06.2021 Acceptance of orders for the supply of a high-speed multi-channel system of non-destructive ultrasonic testing is open.


A data asquisition subsystem for multichannel ultrasonic non-destructive testing (NDT) systems has been developed. We accept applications for the supply of equipment.

Technical characteristics of the subsystem in more detail.




18.03.2019 The development of system for testing VMM ASIC is completed. VMM ASIC is one of a core of new electronics for New Small Wheel (NSW) of ATLAS experiment (CERN).


The obsolete electronics for events registering will be changed to the new during Phase II upgrade of the NSW. The new front-end electronics based on VMM ASIC. VMM is a 64-channels analog-digital integrated circuit.

Parameters of VMM analog blocks can significantly vary from one channel to other both within the same IC and from one chip to another. It could be the reason to get significant differences in response of different channels to the same input stimulus. To ensure the reliability of the measurement results in the ATLAS experiment, it is necessary to evaluate the parameters of each registration channel and apply corrective coefficient for the variance of channels in the data recording system. In addition, it is necessary to perform functional diagnostics of each of all 50 thousand VMMs and sort them according to the health criteria before assembling the printed circuit boards of the recorders.

VMM Tester was developed to perform per-channel diagnostics of VMM ASIC. The tester provides a solderless electrical connection of all ASIC pins, connection of an external test signals generator to all analog inputs of VMM, data transfer for further analysis of measurement results via USB 3.0 and Ethernet (SFP +) interfaces. The tester software sets the VMM operating mode of any of the allowed configurations (or configuration list), starts the test and transfers the results to the computer for the data analysis.

VMM Testers and the corresponding design and software documentation were transferred to the customer (Tomsk State University). Researchers Researchers of TSU have started testing the VMM3 prototype lot.



04.05.2017 HDAccess 3 FMC carrier USB 3.0 board is ready for ordering


The USB 3.0 Capture device (HDAccess 3) has been completed and could be ordered. Hardware is intended for capture different kind of digital data stream and passing it through USB 3.0 interface. It is designed as FMC (FPGA Mezzanine Card) LPC (Low Pin Count) carrier board and has USB 3.0 and SFP (Small Form-factor Pluggable). Captured data flows through FMC. Recognition features, synchronization, and data capture are performed on FPGA, so the device can be configured to capture data of any published or proprietary format.

The device supports the connection of any FMC, compliant VITA 57 (FMC LPC). Supported interfaces are as follow:

  • HD SDI;
  • ASI;
  • HDMI;
  • Video port;
  • Video Sensor;
  • Ethernet;
  • High speed ADC;


15.07.2013 Minerva releases alpha version of UpScaler IP Core


UpScaler IP Core is a compact and high performance realization of the novel picture scaling algorithms. IP Core increases vertical and horizontal picture resolution with any scaling coefficients and is intended for using in video output path to the display device. More info...



25.02.2013 Minerva CABAC Encoder IP Core - Alpha release


29th of March, 2013 - CABAC Encoder IP Core (ver 1.0) is available for evaluation.