The H.265(HEVC) CABAC Decoder IP-Core is designed to perform context-adaptive binary arithmetic decoding operations. The IP-Core can be used as a coprocessor to accelerate video coding or as an integral part of the HEVC video codec in an FPGA or ASIC.
The presentation explores existing high-performance video codec solutions capable of compressing and transmitting video with the highest possible quality over networks or radio channels. The report introduces a highly efficient and compact hardware implementation of the H.264/AVC codec for embedded systems, designed to encode video in real time with low latency. The demonstration will showcase the codec on a developer board based on the FPGA XC7Z020.
This report will be of interest to professionals involved in the development of digital devices in the field of digital video. The conference program is available on the organizer's website.
The low-latency AVC Encoder IP Core is implemented on the Zynq-7000 FPGA family. A product demo is available for PYNQ-compatible development boards. For purchase inquiries, please contact Sales.
The data acquisition system is designed to test the operability of specialized matrix integrated circuits MIC 1024 and hybrid sensor assemblies based on them. The developed system enables performance monitoring of the MIC 1024 chip after each technological stage in creating a hybrid sensor assembly. Operability tests are conducted both on microchips mounted on 150 mm wafers using a manual MPI TS150 probe station, and on microchips installed on a printed circuit board. Detailed technical specifications are available here.
A data acquisition subsystem for multi-channel ultrasonic non-destructive testing (NDT) systems has been developed. Applications for the supply of equipment are now being accepted. Detailed technical specifications are available here.
The obsolete electronics for event registration will be replaced during Phase II of the NSW upgrade. The new front-end electronics are based on the VMM ASIC, a 64-channel analog-digital integrated circuit.
Parameters of the VMM analog blocks can vary significantly from one channel to another, both within the same IC and between different chips. These variations can lead to significant differences in the response of channels to the same input stimulus. To ensure the reliability of measurement results in the ATLAS experiment, it is necessary to evaluate the parameters of each registration channel and apply corrective coefficients to account for channel variance in the data recording system. Additionally, functional diagnostics of all 50,000 VMMs must be performed, and the chips must be sorted according to health criteria before assembling the printed circuit boards of the recorders.
The VMM Tester was developed to perform per-channel diagnostics of the VMM ASIC. The tester enables solderless electrical connection to all ASIC pins, connection to an external test signal generator for all analog inputs of the VMM, and data transfer for further analysis via USB 3.0 and Ethernet (SFP+) interfaces. The tester software configures the VMM to operate in any allowed mode, initiates the tests, and transfers the results to a computer for data analysis.
VMM Testers, along with the corresponding design and software documentation, were delivered to the customer (Tomsk State University). Researchers at TSU have begun testing the VMM3 prototype lot.
The USB 3.0 capture device (HDAccess 3) has been completed and is available for ordering. The hardware is designed to capture various types of digital data streams and transmit them via the USB 3.0 interface. It is implemented as an FMC (FPGA Mezzanine Card) LPC (Low Pin Count) carrier board and features USB 3.0 and SFP (Small Form-factor Pluggable) interfaces. Captured data flows through FMC, with recognition, synchronization, and data capture performed on the FPGA. This enables the device to be configured to capture data in any published or proprietary format.
The device supports the connection of any FMC-compliant VITA 57 (FMC LPC) module. Supported interfaces include:
The UpScaler IP Core is a compact, high-performance implementation of novel picture scaling algorithms. The IP Core enhances vertical and horizontal picture resolution with any scaling coefficients and is designed for use in the video output path to display devices.