H.264(AVC) CABAC Decoder IP Core
CABAC Decoder IP Core performs stream decoding that was derived by context-adaptive binary arithmetic coding algorithms. The IP Core is designed to accelerate the decoding of compressed video AVC (H.264) format.
CABAC Decoder IP Core performs streams decoding that were derived by algorithms CABAC (Context-Adaptive Binary Arithmetic Coding). IP Core is designed for hardware acceleration of entropy arithmetic decoding of AVC (H.264) streams.
Features
- —Fully complies with ISO / IEC 14496-10 / ITU-T H.264
- —Profile: Main
- —High performance. Bit rates — up to 40 Mbit/s at a clock frequency of 200 MHz
- —Hardware initialization and binarization contexts
- —Compact core size. Can be used for FPGA low-price range.
Delivery
The IP Core is available as either a netlist or in source code, and includes everything necessary for a successful implementation of the customer's project.
The netlist includes:
- —Synthesized netlist for the specified FPGA device.
- —Testbench and bit-accurate model.
- —Place-and-route script.
- —Simulation script.
- —Documentation, including detailed specifications and instructions for project integration.
For further technical information:
info@minerva-tech.com
For purchasing or licensing:
sales@minerva-tech.com